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 (R) ISO 9001 Registered
Process C3015
CMOS 3m Digital
Electrical Characteristics
T=25oC Unless otherwise noted
N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTN N N LeffN WN BVDSSN VTFP(N) Minimum 0.6 42 2.85 12 12 Typical 0.8 0.6 47 3.2 0.7 Maximum 1.0 52 3.55 Unit V V1/2 A/V2 m m V V Comments 100x3m 100x3m 100x100m 100x3m Per side
P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage
Symbol VTP P P LeffP WP BVDSSP VTFP(P)
Minimum -0.6 13 2.85 -12 -12
Typical -0.8 0.55 15 3.2 0.9
Maximum -1.0 19 3.55
Unit V V1/2 A/V2 m m V V
Comments 100x3m 100x3m 100x100m 100x3m Per side
Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Gate Poly Sheet Resistance Metal-1 Sheet Resistance Passivation Thickness
Symbol P-well(f) N+ xjN+ P+ xjP+ TGOX POLY1 M1 TPASS
Minimum 3.2 16 50 37.5 15
Typical 4.8 21 0.8 80 0.7 40.0 22 30 200+900
Maximum 6.5 27 100 42.5 30 60
Unit K/ / m / m nm / m/ nm
Comments P-well
oxide+nit.
Capacitance Gate Oxide Metal-1 to Poly-1 Metal-1 to Silicon
Symbol COX CM1P CM1S
Minimum 0.66 0.026
Typical 0.72 0.0523 0.030
Maximum 0.78 0.034
Unit fF/m2 fF/m2 fF/m2
Comments
(c) IMP, Inc.
89
Process C3015
Physical Characteristics
Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Metal-1 Width/Space Gate Poly Width/Space N <100> 15 - 25 -cm 5V P-well 1 1 2.0x2.0m 3.5 / 2.5m 3.0 / 2.5m N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 3.0 / 3.0m 12m 2.5m 1.5m 1.0m 1.0 m 100x100m 5.0m 80.0m
Special Feature of C3015 Process: 3 m P-well digital process.
Second metal
Poly gate
A1
SIO2 LTO
p+
p-well contact
n+
Drain
n+
source
SIO2 p
p+
Drain
p+
Source
n+
N- substrate contact
Field Oxide
Sidewall spacer Bottom poly Poly gate Contact
p
p
p-well
n-epi N+ substrate
Cross-sectional view of the C3015 process
ID vs VD, W/L = 20/4.0
5 VGS = 10V 4 VGS = 9.0V VGS = 8.0V 3 VGS = 7.0V VGS = 6.0V VGS = 5.0V 1 VGS = 4.0V VGS = 3.0V VGS = 2.0V 56 78 9 10 34 Drain Voltage (v), VDS n-ch Transistor IV Characteristics of a 20/4.0 device 1 2 0 0 0 0 1 Drain Current (mA) IDS -2.5 -3
ID vs VD, W/L = 20/4.0
Drain Current (mA) IDS
-2
VGS = -10V VGS = -9.0V VGS = -8.0V VGS = -7.0V VGS = -6.0V VGS = -5.0V VGS = -4.0V VGS = -3.0V VGS = -2.0V 10
-1.5 -1
2
-.5
2
78 56 34 Drain Voltage (v) VDS
9
p-ch Transistor Characteristics of a 20/4.0 device
90
C3015-4-98


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